1. Technical Field
The present invention relates to a semiconductor storage device.
2. Related Art
Semiconductor storage devices of the related art are disclosed, for example, in Japanese Laid-open Patent Publication No. H11-7776. As shown in FIG. 5, the semiconductor storage device disclosed in the same document is equipped with an SRAM cell constructed from six transistors 101 to 106. Namely, in addition to four transistors 101 to 104 constituting a latch circuit, the SRAM cell also has two pass transistors 105, 106 provided between the latch circuit and bit lines on either side. Further, a semiconductor storage device with pass transistors provided doubly is disclosed in Japanese Laid-open Patent Publication No. H8-7574.
Typically, in a SRAM cell, in order to obtain the necessary cell ratio, it has been necessary to carry out design in such a manner that the power (current-drive power) of pass transistors is lower than that of drive transistors, namely, N-type FETs (Field Effect Transistors) constituting a latch circuit. Here, “cell ratio” is the power ratio of a drive transistor and a pass transistor. Adjustment of the cell ratio can be carried out, for example, by adjusting the threshold voltages of these transistors. However, in this case it is necessary to introduce impurities under different conditions for a pass transistor and a drive transistor and manufacture of a semiconductor storage device therefore becomes complex.
Further, as shown in FIG. 6, adjustment of the cell ratio can be carried out by adjusting the gate length and the gate width of these transistors. The same drawing is a plan view of the SRAM cell corresponding to the circuit of FIG. 5. In the same drawing, a gate length L2 of the pass transistors 105, 106 is designed to be larger than a gate length L3 of the drive transistors 102, 104. Further, a gate width W2 of the pass transistors 105, 106 is designed to be smaller than a gate width W3 of the drive transistors 102, 104.